updated 09:45 am EDT, Tue October 23, 2007
Samsung 30nm Flash
Samsung late Monday announced that it had produced the world's first working NAND flash memory based on a 30-nanometer manufacturing process, promising a greatly increased storage density over today's chips. The smaller manufacturing technique was made workable through a new technology known as self-aligned double patterning. By stepping up the use of lithography, the company is able to write both a coarser, more conventional pattern of memory cells as well as a finer pattern that fills the gaps; this makes the best use of the available space, Samsung says.
In a high capacity, multi-level cell (MLC) flash design, the improvement should allow for 64-gigabit chips that can combine to produce a 128GB memory unit; this would hold as much as 32,000 songs or 80 full-length movies at DVD quality, according to the company. A simpler single-level cell (SLC) design would store half the data at 32 gigabits (64GB for complete storage) but would be faster and longer-lasting. Either design, however, is said to be less expensive to make as the use of lithography speeds up manufacturing and reduces the effective cost for each complete chip.
Samsung said it expected to commercialize the 64-gigabit NAND chips, and likely 128GB memory units, sometime in 2009. No mention was made of when the 32-gigabit technology would enter production or what physical size either memory unit would require, which may limit the available storage in different device classes; at least camcorder storage and solid-state hard drives for notebooks were certain, though the company's reference to media storage also alluded to portable media players.
If usable in a smaller form factor, the storage would represent an eightfold boost to flash capacity in two years over current flash-based media players, which top out at 16GB in devices such as the Creative ZEN and Apple iPod touch. Flash is generally expected to replace hard drives over time as the lack of moving parts and thinner profile will help improve the performance and reliability of devices while also reducing the practical size.