Intel provides more Nehalem details

The upcoming Nehalem processor design will not just be an upgrade to existing processors but a complete replacement for the Core architecture, Intel has explained as part of a press briefing. It will be built on the same 45 nanometer manufacturing process as today's Penryn architecture but is designed to be extremely scalable: in addition to scaling from as few as two cores per chip to as many as 8, Nehalem can be optimized to run efficiently in notebooks or at full speed for servers and workstations.

The QuickPath architecture is also crucial to the design. Rather than implement a traditional front side bus (FSB) for the system, the Quickpath architecture provides a direct link to key components and avoids the bottlenecks that affect current architecture. At 25.6GB per second, the bandwidth of the fastest Nehalem processors will be more than four times that of Penryn, the company notes.

Changes to the design will also significantly reduce the amount of needed cache memory while still improving performance. Most versions will include an integrated memory controller and sport no more than 256KB of cache per core versus the 6MB or more used today; by reducing the lag time for processing instructions, Nehalem is said to require less memory for a similar or better result. Example processors are also said to have 64KB of total Level 1 cache for data and instructions and will support faster grades of DDR3 RAM up to 1,333MHz.

The first versions of Nehalem are expected to ship sometime in late 2008 and will likely be used first for high-end Xeon systems from Apple, Dell, HP, and other major manufacturers. Mainstream desktops and notebooks based on the new design are expected by early 2009.