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AMD, HP propose more efficient PCIe 3.0 specs

updated 01:20 pm EDT, Fri July 31, 2009

AMD, HP PCIe 3.0 changes

Extensions proposed by chip maker AMD and computer builder HP could greatly improve the efficiency of the draft PCIe 3.0 specification, a report notes. One contribution involves protocol multiplexing, which would let chips switch between as many as seven different protocols beyond PCIe. As a result, interfaces could use fewer pins, and PC makers could build more flexible configurations with fewer components. A single part could handle PCIe, Quick Path Interconnect and the coherent HyperTransport bus, for instance allowing simpler offloading of CPU tasks to accelerators like video cards.

The other extension, lightweight notification, would permit co-processors or peripheral chips to communicate with each other through system memory, avoiding host processor interruptions. A given example is an Ethernet switch, which could be made to handle encryption and decryption while leaving a host processor inactive. Either extension could be used with the 2.5, 5 and 8GHz variants of PCIe.

The draft PCIe 3.0 specification is set to be published by June. Practical products are not forecast to arrive until 2012 or 2013.



By Electronista Staff
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