updated 06:15 pm EDT, Tue August 11, 2009
Next-gen DRAM developed
Semiconductor Research Corporation (SRC) together with researchers at Yale University researchers on Tuesday announced they have found a way to significantly increase performance of DRAM chips. The improvements stem from using ferroelectric layers that no longer requires the use of a storage capacitor found in conventional DRAM cells. Called Ferroelectric DRAM (FeDRAM), the cells would have a cell structure that closely resembles that of a CMOS transistor, with ferroelectric rather than dielectric gates.
Specific advantages are said to include improved scalability, smaller cell size, a minimum of 1,000 times more retention time and lower power consumption. There is also the possibility of storing multiple bits per cell, such as in flash memory chips. Manufacturing such chips would also be less complicated and therefore less costly.
The researchers are now focusing on creating working prototype FeDRAM cells along with simple building block circuits and pathways for scaling. With support of other SRC member companies, production FeDRAM chips may come to market in the not-too-distant future, though no particular timetable has been given.