IBM has just yesterday introduced its next generation RISC CPU, the Power7. The new chip will continue to be used in IBM's AIX Unix operating systems for servers, supports the IBM i operating system and can run Linux natively or in an x86 binary translation code. Noteworthy benefits of the new chip include an increase in the number of cores and the performance per core. There is now eight cores, with each capable of four simultaneous multithreading threads. SMT will reduce wait periods of software for resources to free up.

Compared to the current Power6 chip, the Power7 CPU has higher performance at lower frequency. Apart from adopting SMT, Power7 also added out-of-order execution, which was present in the company's early chips but failed to make it into the Power6 lineup. This allows instructions that are waiting for processing to be skipped over until they are ready.

Bandwidth was increased via dual DDR3 memory controllers for a total of 100GBps of sustained memory bandwidth per chip. Integrated scalability ports total 32 sockets with 360GBps SMP bandwidth per chip. There's also 32MB of shared Level 3 (L3) cache in the middle of each chip, which is physically much closer than in the past, where IBM placed it on a separate multi-chip module for faster speeds due to the closer proximity. The L3 cache is also the first in a commercial processor to use embedded DRAM (eDRAM) which requires one transistor per device, unlike the more commonly used static RAM (SRAM), which requires six transistors but is faster and doesn't need constant refreshing. IBM claims the memory refreshes are done during what it calls "windows of opportunity," and is therefore almost as fast as SRAM arrays.

Power consumption has also been addressed, with the sleep mode using up the minimum level required to retain state.

To increase reliability, IBM used X8 chip-kill with 64-byte error correcting code. Key system partitions can be mirrored, like in a RAID 1 configuration. Power7 also improves upon its predecessor's error-checking and failover capabilities.

The Power7 chips are expected to come to IBM-powered systems sometime in mid-2010. [via CNET]