AMD sheds more light on Bulldozer processor architecture
updated 11:00 pm EDT, Tue August 23, 2011
Slides show Zambezi for AM3+ platform
AMD has disclosed a number of fresh details surrounding its upcoming Bulldozer processor cores, along with the AM3+ platform. Presentation slides show a Bulldozer die with eight AMD64 cores and 8MB of L2 cache, two 72-bit DDR3 memory channels and four 16-bit receive/16-bit transmit HyerTransport links. The new architecture splits eight cores across four Bulldozer modules, each with two integer cores and a floating point core.
The AM3+ socket architecture adds support for low-voltage DRAM, increased current for higher frequency HyperTransport connections and two memory channels. The sockets will be backwards-compatible with older AM3 processors, though it is designed for use with 9-Series chipsets.
The slides also demonstrate Bulldozer's capabilities with Turbo Core. The system enables increased clock speeds across all cores when there is TDP headroom. If a lightly threaded workload places half of the modules into sleep state, the chips can still run increase clock speeds for the active cores when necessary.
The first Bulldozer chips are expected to arrive before the end of the year, however AMD has yet to announce specific launch dates. [via Tom's Hardware and ComputerBase]
