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AMD's Steamroller CPU architecture detailed, due in 2013

updated 11:55 pm EDT, Tue August 28, 2012

Bulldozer update refines multiprocessing, streamlines floating point

Tuesday at the Hot Chips Symposium, AMD's Chief Technology Officer Mark Papermaster unveiled AMD's upcoming CPU core. The new core, called Steamroller, is the third generation of the chip manufacturer's Bulldozer architecture and uses a 28nm manufacturing process. Steamroller is the first major refresh of the architecture of the CPU, and according to the presentation increases performance by 15 percent with equivalent power and clock speed.

AMD calls the new architecture "no compromises two thread performance," but is in actuality a nod to previous dual-core implementations. One of the limitations of the original Bulldozer architecture is in the fetch/decode hardware. Bulldozer can only decode four instructions per processor, for a maximum of 16 instructions in a four module/eight core build. Sandy Bridge Intel processors can process 4 instructions per core, rather than per module, allowing for 32 decodes per eight-core CPU. The new design meets the Sandy Bridge and Ivy Bridge 4 instructions per core limit, presumably gaining in performance with this improvement alone.

The floating point module and calculator has "streamlined execution hardware" suggesting that the instruction set, and accordingly, the part of the die responsible for floating point calculations, has been reduced somewhat to accommodate the dual decode units in the processor. AMD's current pipeline and roadmap for future development suggests that a graphical processing unit, either on the motherboard or a discrete PCI-E card, will do most of the floating point calculations so a reduction in on-chip capability may not be an issue for the Steamroller design. AMD's market segment of primarily home users generally doesn't require on-die peak FPU performance. The preponderance of home users needing rapid FPU performance is gamers, and that market segment is accommodated by AMD's graphic processing unit division.

Steamroller is expected to ship in 2013. Intel's fourth generation of the Intel Core processor architecture "Haswell" is based on the 22nm manufacturing process, and is expected at retail in the second quarter of 2012, with rumors placing it in April. The first chip on the public roadmap to integrate the Steamroller core is the Kaveri system-on-a-chip, but no launch date has been announced. [via Hot Hardware]

By Electronista Staff
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    Joined: 04-07-00

    Actually Sandy Bridge can decode 5 instructions per cycle in extreme corner cases (by using macro-ops fusion), and AMD is still missing the third ALU/core from Phenom, so it will still not be on par with Intel. I'm all for this renewed focus on single-threaded performance, but I don't see why they didn't just add 4 more decoders to the single block to give it some flexibility in assigning them.

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