NEC LaVie first to tout Intel 'Haswell' CPUs, beats Intel to the punch
The NEC LaVie L has surfaced on the NEC Japan website and is one of the first notebooks to feature Intel’s next-generation ‘Haswell’ processors. The new chips will carry the ‘Core’ branding and will be available in Core i3, Core i5 and Core i7 variants as it has in its previous three generations. NEC has ‘jumped the gun’ somewhat in revealing the specs of the new notebook with Intel not expected to formally launch the chips until Computex Taipei in early June.
Early Haswell devices will use the flawed chips despite problem
Following some earlier reports, Intel has confirmed a bug exists in the silicon of its next-generation Core processor dubbed "Haswell." The bug can cause USB 3.0 devices to vanish after entering a low power state, with the device generally having to be disconnected and reconnected for the file structure to reappear.
Mobile, low-power processors focus of Intel event
Intel has demonstrated its fourth generation of Core processors at the company's CES press event. The demonstration also gave the chip maker a chance to demonstrate a new quad-core 22nm Atom System-on-Chip processor it calls "Bay Trail," as well as low-powered versions of existing architectures and processors aimed towards developing nations.
Chart shows plans for Haswell architecture in 2013
Details on Intel's Haswell processor family have been relatively scarce since the company formally announced the line in September, but now a document has emerged that appears to reveal Intel's plans for the processor line next year. The next year should see the release of at least 14 new desktop CPUs, topping out at a 3.5GHz Core i7 with the potential for 400MHz more in Boost Mode. That model would be operating across four cores and eight threads.
Latest low-power design in the 'Core' family of processors
Opening the 15th Intel Developer Forum in San Francisco, Intel Chief Product Officer Dadi Perlmutter unveiled the new "Haswell" processor family. The keynote speech demonstrated test systems running the fourth-generation Core processor, based on the same 22nm process used in the third-generation Ivy Bridge family of processors.
Intel Haswell to lower ultrabook power, up others
First details of Intel's Has well architecture has emerged through presentation slides leaked [reg. required] through ChipHell. The 22-nanometer design will focus most on Intel's promises of more advanced ultrabooks and will lower the peak power of a dual-core, low-voltage chip to 15W, helping battery life in systems like the MacBook Air. It should also support low-power DDR3 memory and get integrated GT3 graphics that, like on Sandy Bridge, are faster than on the desktop.
Intel Haswell to make huge strides in battery life
Intel at its Developer Forum provided more details about its Haswell processor foundation for 2013. Although 22 nanometers like the Ivy Bridge design due early next year, it will be much more power efficient than an existing chip. The company plans for a 30 percent reduction in active power use over a modern Core i5 and that notebooks could last a complete 24 hours on a charge without needing extended cells, competing with ARM tablets.
Intel ultrabook idea based on MacBook Air concept
Intel's Sean Maloney opened Computex in earnest with a keynote hoping to redefine the ultraportable notebook class. Now calling them "ultrabooks," Intel saw them as systems that were under 0.8 inches thick but could still start under $1,000. The category included systems like the ASUS UX21 and, by extension, the MacBook Air.
Intel 2009-1010 Leaked Map
Intel's upcoming processor generations will double the number of cores per chip and add a brand new language for specialized code, according to leaked slides obtained by CanardPlus. Although the semiconductor company's Core i7 will just receive a manufacturing process shrink down from 45 nanometers to 32 during 2009, reducing its power use and allowing more complex parts, a replacement architecture codenamed Sandy Bridge will replace it by 2010 and double the number of cores per die to eight. Hyperthreading support will let it handle as many as 16 code threads at once, while a large 16MB pool of Level 3 cache will be shared to make best use of the cores.